The present invention relates generally to semiconductor dies, and more specifically, to vias used in semiconductor dies.
A semiconductor die includes various metal layers in which metal lines are formed. The metal lines are used for routing electrical signals such as logic signals, clock signals, and power lines. Metal lines in the same plane are placed at a predetermined pitch from each other. The metal lines in alternate metal layers are perpendicular to each other.
Vias are used to connect a metal line from one metal layer with a metal line in another layer. FIG. 1 illustrates a conventional via structure in a semiconductor die 102. The semiconductor die 102 includes a plurality vertical metal lines such as vertical metal lines 104a, 104b, and 104c; a plurality of horizontal metal lines such as a metal line 106; and a via 108. The vertical metal lines 104a, 104b, and 104c are located in a first plane and the horizontal metal line 106 is located in a second plane, which is adjacent to and above (or below) the first plane. The via 108 connects the horizontal metal line 106 with the vertical metal line 104a. The width (w2) of the horizontal metal line 106 is greater than the width (w1) of the vertical metal lines 104a, 104b, and 104c. Therefore, the via 108 causes the adjacent vertical metal lines, 104b and 104c, on both its sides to detour in order to maintain the predetermined pitch. This detouring wastes routing space. Further, since the semiconductor die 102 will contain many vias, there is a considerable waste of die area. This in turn causes an increase in the die size and thus an increase in die cost.